Phase shift keying in the form of BPSK and QPSK have been used for almost as long as there has been a need to transmit digital information. For the most part, PSK demodulators have been implemented in the past with mostly analog technology. Analog technology suffers from a number of limitations. In particular, the matched filter for an analog demodulator must be designed for a specific symbol rate. If a demodulator must process a number of symbol rates, one analog filter for each symbol rate must be included in the demodulator design. Analog techniques can be implemented which permit frequency tuning, but such a design will involve a number of different components and several analog adjustments. Any analog design will be sensitive to normal analog component tolerances as well as component imperfections such as DC bias, spurious components, unwanted bandlimiting effects and imbalance between signal paths which should be closely matched.
In the past few years, semiconductor technology has progressed to the point where many tens or hundreds of thousands of gates can be resident on a single CMOS integrated circuit. This technology has made it practical to implement all of the signal processing algorithms of a PSK demodulator on a single chip. Aside from the cost benefit of such a solution, digital techniques are capable of overcoming all of the above mentioned limitations of analog technology. Low data rate digital demodulators have been implemented using programmable digital signal processing (DSP) devices. A number of demodulator integrated circuits have been developed which permit digital data (such as FAX) to be transmitted over conventional telephone lines.
Recently, satellite technology has been used to broadcast digital information at high rates to a large number of subscribers. In particular, direct broadcast satellites (DBS) will be used to transmit digital television signals to subscribers which utilize a small, low cost terminal. Also planned are services for satellite broadcast of digital CD quality audio. All of these broadcast services require a low cost, digital demodulator capable of demodulating data rates in the range of several hundred kilobits-per-second to several tens of megabits-per-second.
A number of components required of a digital demodulator have been developed and made available commercially. In particular, these consist of a variety of direct digital synthesizers (DDS) products and digital down converters and digital symbol tracking devices. Currently, a number of disclosures have appeared intended to improve the BPSK/QPSK demodulation process.
For example, U.S. Pat. No. 4,344,178 to Waters discloses a decision-directed Costas loop demodulator which operates on a slowly varying error signal rather than on the rapidly varying I and Q channel signals.
U.S. Pat. No. 5,117,195 to Robbins discloses a demodulator for recovering multiphase modulated digital data from an analog carrier which features a shift register that samples the input waveform at a clock rate that is a multiple of the carrier frequency and resolves the digital waveform into two components for the purpose of QPSK analysis.
U.S. Pat. No. 4,180,779 to Hook et al discloses a QPSK demodulator utilizing a bandpass filter separating two doubling units which allow use of heterodyning in order to operate at a lower frequency.
U.S. Pat. No. 5,103,466 to Bazes discloses a clock and data recovery circuit information from phase encoded serial data including a synchronous delay line.
U.S. Pat. No. 4,606,051 to Crabtree et al discloses a modem receiver including FIR filters which perform quadrature detection
U.S. Pat. No. 4,612,518 to Gans et al discloses a QPSK modulator or demodulator using a carrier frequency which is a subharmonic of a predetermined microwave carder frequency.
U.S. Pat. No. 4,501,002 to Auchterlonie discloses an offset QPSK demodulator which samples inphase and quadraphase channels and derives carder phase and clock phase signals even if the samples are hard limited.
U.S. Pat. No. 4,414,675 to Comroe discloses a demodulator with a limiter for amplitude limiting the data signal and a microcomputer for having an interrupt routine which extracts the clock offset to provide an estimate of the relative location of the bit boundaries.
U.S. Pat. No. 5,179,578 to Ishizu discloses a demodulator including a .pi./4 phase shift circuit in a conventional QPSK Costas loop to alternately rotate the phase of an inputted QPSK signal.
U.S. Pat. No. 5,268,647 to Ichiyoshi discloses a method and apparatus for coherently demodulating PSK signals using a feedback loop including a filter bank.
U.S. Pat. No. 4,773,083 to Baumbach et al discloses a demodulator for QPSK including one optimizer which adjusts the phase of a reference signal used for modulating the QPSK into baseband in-phase and quadrature channel components and another optimizer which adjusts a sampling clock used to sample and quantize the baseband channels.
U.S. Pat. No. 4,814,719 to Guyer discloses a demodulator in which the amplitudes of the I and Q signals are different and have been modulated by signals having different bit rates.
U.S. Pat. No. 4,833,416 to Attwood discloses a demodulator including a pseudo data estimation loop for reducing loop gain variation.
None of the demodulators disclosed in this cited art is amenable to consolidation of the demodulator into a single chip having VLSI architecture, which adds to the expense of the demodulator and limits operating speed and increases power consumption. Furthermore, those devices in the prior art employing a digital FIR filter, operate on a fixed ratio between the input sample rate and filter output rate which limits demodulator efficiency and also limits symbol rate of the processing signal.